CMOS Design > Memories Précedant suivant

Classification

A summary of CMOS embedded memory performances is given in table 10-2. The typical memory bank capacity gives an advantage to the ROM, EPROM, EEPROM and Flash memories, which is directly correlated with the cell area. The reading and writing performances vary very significantly, as well as the retention of data. Dynamic RAM (DRAM) are slow but compact. Static RAM (SRAM) are fast but large. Reading the information from a passive capacitor, such as in DRAM, is much slower that reading the information from the active inverter-based memory such as in SRAM. In contrast, a single trench of stacked capacitor requires much less silicon surface than a 2-inverter memory structure, at the cost of 8 supplementary process steps. The FLASH memories combine a small area, an acceptable reading cycle and interesting non-volatile capabilities, at the price of a slow writing process (1µs). Promising performances are achieved by ferroelectric RAM (FRAM) which are the most advanced of non-volatile challengers. FRAM have endurance writing/erasing cycles comparable to the best memories, with fast reading and writing cycles, and require only two additional process masks.

Memory type Typical Capacity Cell area Reading Writing Cycles Retention Process complexity High voltage
ROM 32Mb Very small Medium Impossible 0 No limit 0 no
EPROM 16Mb Very small Slow Extremely slow 1-10 >30 YEARS 3 yes
E2PROM 1Mb Large Slow Very slow 1E5-1E7 >10 YEARS 4 no
FLASH 16Mb Very small Medium Very slow 1E4-1E5 >10 YEARS 4 yes
FRAM 4Mb Small Fast Fast 1E12-1E15 >10 YEARS 2 no
eDRAM 32Mb Small Slow Fast >1E15 Volatile, needs to refresh 8 no
SRAM 4Mb Large Very fast Very fast >1E15 Volatile 0 no
Table 10-2: A classification of embedded memories according to their performances


CMOS Design > Memories > Classification Précedant suivant