Inverter Behavior

The CMOS inverter design is detailed. Here one p-channel MOS and one n-channel MOS transistors are used as switches.

When the input signal is logic 0, the nMOS is switched off while PMOS passes VDD through the output, which turns to 1. When the input signal is logic 1, the pMOS is switched off while the nMOS passes VSS to the output, which goes back to 0. The n-channel MOS symbol is a device that allows the current to flow between the source and the drain when the gate voltage is "1".

The analog simulation of the circuit is performed.

The truth-table is verified. A logic zero corresponds to a zero voltage and a logic 1 to a 1.20V.

In 0.25µm typical commutation delay 50ps
Depends on computing conditions (10%-90% or 50%)
Depends on charge (output parasitic or real capacitance)

The inverter delay is significantly increased.

It can be seen that the gate delay variation with the loading capacitance is quite linear.