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MOS Design Rules

N-channel MOS

The narrow box in polysilicon layer should not have a width inferior to 2 λ. The N+ diffusion should have a minimum of 7 lambda on both sides of the polysilicon gate. The intersection between diffusion and polysilicon creates the channel of the nMOS device.



P-channel MOS

The narrow polysilicon box to create the p-channel MOS gate should have a width ≥ 2 λ

The P+ diffusion should have a minimum of 7 λ on borh sides of the polysilicon gate. Add an n-well region that completely includes the P+ diffusion, with a border of 6 λ, as illustrated below.



Inverter with same nMOS and pMOS sizes

Using the same default channel width (0.6µm in CMOS 0.12µm) for nMOS and pMOS is not the best idea, as the p-channel MOS switches half the current of the n-channel MOS.

If Wnmos=Wpmos and Lnmos=Lpmos, Ids(Nmos) is proportional to µn while Ids(Pmos) is proportional to µp. Typical mobility values are given below.

for electrons (µn) : 1350 cm2/V·s
for holes (µp) : 480 cm2/V·s

Consequently, the current delivered by the n-channel MOS device is twice the one of the p-channel MOS. Usually, the inverter is designed with balanced currents to avoid significant switching discrepancies. In other words, switching from 0 to 1 should take approximately the same time as switching from 1 to 0. Therefore, balanced current performances are required.

The reason for this addition of contacts is due to the intrinsic current limitation of each elementary contact plug. One single contact can suffer less than 1mA current without any reliability problem. When the current is stronger 1mA, the contact can be damaged. A very strong current (around 10mA) destroys immediately the contact.

The contact is 2x2 λ, and the separation is 3 λ.

  • Minimize drain/source area
  • Use L minimum
  • 1 contact = 1mA
  • Multiply contacts

A good design consists in creating a p-channel MOS with twice the width of the n-channel MOS. The pMOS current is doubled, and becomes comparable to the nMOS current. The behavior will be balanced in terms of switching speed.

  • Same N and P alters symmetry
  • L min
  • Wpmos=2 Wnmos

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