CMOS Design > MOS Modeling Précedant suivant

MOS Model 3

The MOS model 3 is slightly more complicated than model 1. We show here some of the most important equations. We introduce several limiting parameters that affect the transconductance Keff, the efficient LEFF, and the saturation Vsat. The Vdsat equation is a typical fitting curve between Vc and Vsat.


Lateral Drain Diffusion

The lateral drain diffusion (LDD) vis a small low-doped diffusion on both sides of the gate, that prevents from hot carrier parasitic currents. Without, electrons are so accelerated during their transport beneath the gate that they create by impact a pair or elections and holes. Electrons are added to the Ids current while holes are evacuated to the substrate. The LDD limits this effect, which becomes negligeble at normal voltage supply. The hot carrier effect reappears at 1.5 to 2 VDD.


The MOS model 3 requires a large number of parameters. We give here the most important ones. The physical parameters of Level 1 reappear, as well as new paarameters such as LD, PHIN, NSS, VMAX. Not all these parameters have a physical origin. Some of them are just empirical parameters.

Several screens may be proposed:

Current versus drain-source voltage

Using the display mode "Id vs. Vd", you may see the effect of parameters U0, TOX, KAPPA and VMAX. Basically, the carrier mobility U0 moves the whole curve, as it impacts in an almost linear way the current Ids. As U0 is nearly a physical constant, a significant change of mobility has no physical meaning. The oxide thickness TOX does the same but in an opposite way.

Demonstration of the role of U0, KAPPA and VMAX in Id./Vd
(W=10µm, L=0.12µm)

A TOX increase leads to a less efficient device, with less current. KAPPA changes the slope of the current when Vds is high, corresponding to the saturation region. Finally, VMAX truncates the curves for low values of Vds, to fit the transition point between the linear and the saturated region.

Current versus gate voltage

The role of VTO and GAMMA can be observed in the figure below, using the display mode "Id vs. Vg". If we use a long channel device, that is a length much greater than the minimum length, the second order effects are minimized. Act on VTO cursors in order to shift the curves right or left, and GAMMA to fit the spacing between curves. U0 and TOX have also a direct impact on the slope for high Vgs.

.The effects of VTO and GAMMA are illustrated in Id/Vg mode voltage (W=10µm, L=0.12µm)

Now we focus on a short channel MOS device, for example W=2µm, L=0.12µm. Using the same display mode Id vs. Vg, we obtain similar curves as for long-channel device. We observe that the shape of the current is bent. This modification is due to short channel parasitic effects. The parameter THETA is used to bend the current curves at high VGS. The MOS model 3 do not provide parameters to account for the VTO dependence with length.

Current vs Vg in logarithmic scale

We finally illustrate the role of NSS in the display mode "Id(log)/Vg". The parameter NSS has a direct impact on the slope in sub-threshold mode, that is for Vgs<VTO.

In sub-threshold region, the Id dependence on Vgs is exponential. The slope is tuned by parameter NSS. The whole curve is shifted using VTO voltage (W=10µm, L=0.12µm)


CMOS Design > MOS Modeling > MOS Model 3 Précedant suivant