Pad Ring Structure

Core/Pad Limitation

When the active area of the chip is the main limiting factor, the pad structure may be designed in such a way that the width is large but the height is as small as possible. In that case, the oversize due to the pads is minimized. Protections are placed on both sides of the pad area. This situation is often called "Core Limited", and corresponds to the design shown in the figure below. In most pad libraries, the core limited structures have a minimum height, which often implies to place the protection circuits on both sides of the pad.


Chip size fixed by the core

When the number of pads of the chip is the main limiting factor, the situation is called "Pad Limited", and corresponds to the design shown in the figure below. The pad structure may be designed in such a way that the width is small but the height is large. In that case, the oversize due to the pads is minimized. Protections are placed under the pad area.


Chip size fixed by the number of pads

The spared silicon area may be avoided by using a double pair of I/O pads, as illustrated in figure 14-64. This attractive feature has been made available starting 0.25µm technology. An example of a test-chip using a double pad ring is reported that figure, which corresponds to a CMOS 0.18µm test-chip fabricated by ST-Microelectronics for research purpose. The pad pitch is significantly reduced thanks to the double row of bonding pads. The pad pitch for a single row is the sum of the minimum pad width Rp01 and the pad distance Rp02. In the double ring structure, the pad pitch is divided by a factor of 2.

When the chip is pad limited, an interesting feature introduced in 0.18µm technology is the double ring of i/o pads. The pad pitch is twice smaller than a single pad ring, at the price of a little increase in the pad height.