| CMOS Design | |
An illustration of the frequency increase with the technology scale down is proposed using a ring oscillator made from 5 inverters. This very simple circuit has the property to oscillate naturally. We observe the oscillating output and measure its corresponding frequency.
Although the supply voltage (VDD) has been reduced (VDD is 5V in 0.8µm, 2.5 in 0.25µm, 1.2V in 0.12µm), the gain in frequency improvement is significant.
Let us consider the ring oscillator with an enable circuit, where one inverter has been replaced by a NAND gate to enable or disable oscillation. The schematic diagram is shown below, as well as its layout implementation. We analyze the switching performances in high speed and low leakage mode, by changing the properties of the option layer which surrounds all devices.
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| CMOS Design > Inverter > Ring Oscillator | |