| CMOS Design > MOS Modeling | |
Historically, the MOS model 1 was the first to be proposed by Shockley, in 1952. The equations of the MOS level 1 give the evaluation of the current IDS between the drain and the source as a function of VD, VG and VS. The device operation is divided into three regions: cut-off, linear and saturated.
The basic SPICE parameters for model 1 are listed in this table : the threshold voltage VTO, the transconductance KP, the channel width and length, as well as two parameters linked to the VTO modulation : GAMMA and PHI.
A SPICE netlist consists of a text, as shown below. The letter "M" means MOS device. The star "*" adds a comment. The ".MODEL" keyword is used for listing the parameters.
| SPICE parameter | Unit | Value in 0.8µm | Value in 0.25µm | Description |
|---|---|---|---|---|
| VTO | V | 0.8 | 0.5 | Threshold voltage |
| KP | A/V2 | 500 | 250 | Transconductance |
| W | µm | 1.6 | 0.5 | Channel width |
| L | µm | 0.7 | 0.25 | Channel length |
| GAMMA | V1/2 | 0.4 | 0.4 | Threshold dependancy with Vsbstrat |
| PHI | V | 0.7 | 0.7 | Surface potential |
SPICE File :
| MN1 0 6 3 0 TN W= 3.60U L= 1.20U MP1 1 6 3 2 TP W= 9.60U L= 1.20U |
| *n-MOS Model 1 : .MODEL TN NMOS LEVEL=1 VTO=0.70 KP=80.000E-6 GAMMA=0.400 PHI=0.700 |
| *p-MOS Model 1: .MODEL TP PMOS LEVEL=1 VTO=-0.76 KP=25.000E-6 GAMMA=0.400 PHI=0.700 |
In the Id/Vg curve, we extract the threshold voltage. In the previous chapter we observed the parasitic effects due to this threshold. Analog design is much concerned by an accurate prediction of the threshold voltage.
The role of VTO, GAMMA and PHI can be observed in the figure. Act on VTO cursors in order to shift the curves right or left, and GAMMA and PHI to fit the spacing between curves. KP acts on the slope.
In the Ids/Vds curve, the current Ids is plotted for varying gate voltage Vgs, from 0 to VDD. The parameter Ion gives the maximum available current, corresponding to maximum voltage Vds and Vgs. Ion is a very important parameter for signal switching, for example in logic gates.
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| The model 1 predict a current 5 times higher than the measurement in the case of a large channel MOS device (L=10µm). |
These old equations (1968, in [Shichman]) are not acceptable in 0.12µm. If we consider MOS devices with very long length (L>10µm), the mismatch between the simulation and the measurement is the order of a factor of five. Let us compare the simulation and the measurement, for a device with a width W=10µm, and a long channel length L=10µm, fabricated in 0.12µm CMOS technology, as presented in figure. The measurement "Ne10x10.MES" was downloaded using the button "Load Measurement". This measurement corresponds to a n-channel MOS device with a channel width 10µm and length 10µm, fabricated in CMOS 0.12µm from ST-microelectronics.
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| Comparing measured Id/Vd and level 1 simulations for a 10x10µm device result in a surprising similarity (Ne10x10.MES). |
Initially, the simulation and measurement do not correspond at all. The mobility U0 needs to be decreased from its initial value 0.06 down to 0.01. The curves are fitted at the price of an unrealistic change in the mobility parameter.
When dealing with sub-micron technology, the current predicted by model "Level 1" is several times higher than the real-case measurements. This means that several parasitic effects appeared with the technology scale down, most of them tending to reduce the effective current compared to the early modeling equations of the model 1.
| CMOS Design > MOS Modeling > MOS Model 1 | |