Sample and Hold Circuit

Sample and Hold (S/H) circuits are critical in converting analog signals to digital signals. Its main function is to capture the signal value at a given instant and hold it until the ADC can process the information.

The transmission gate can be used as a sample and hold circuit.

When the gate is off, the value of the sampled data remains constant. This is mainly due to the parasitic capacitance C_Load of the node, which has a value of 0.8 fF, as extracted in a CMOS 0.12µm process.

Ron and Cload adjust the bandwidth of the system.

Advises to design the sample and hold circuit:

PMOS and NMOS have same size to compensate parasitic capacitances: CGS/CGD
PMOS must switch before the NMOS to compensate the higher mobility of elections in NMOS

The layout of the transmission gate is reported figure.

When sampling, the transmission gate is turned on so that the sampled data DataOut reaches the value of the sinusoidal wave DataIn.

The operation is repeated in time with a regular sampling period.

We can notice that during the sampling period, the S/H circuit operates in dynamic mode (sample) and the in static (hold) mode.

The critical element in accurately capturing the analog input voltage is the number of sampled data in the considered time window. We can also talk about the sampling frequency compared to the input voltage frequency. The Shannon's Sampling Theorem gives the minimum frequency required to accurately represent the analog input voltage:

Shannon's Sampling Theorem:

The minimum sampling frequency must be equal to or greater than twice the highest frequency component of the original signal. To be strictly accurate we should use the term "Bandwidth" rather than highest frequency component.