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CMSIS-CORE
Version 3.00
CMSIS-CORE support for Cortex-M processor-based devices
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Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Data Fields | |
| union { | |
| __O uint8_t u8 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. | |
| __O uint16_t u16 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. | |
| __O uint32_t u32 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. | |
| } | PORT [32] |
| Offset: 0x000 ( /W) ITM Stimulus Port Registers. | |
| uint32_t | RESERVED0 [864] |
| Reserved. | |
| __IO uint32_t | TER |
| Offset: 0xE00 (R/W) ITM Trace Enable Register. | |
| uint32_t | RESERVED1 [15] |
| Reserved. | |
| __IO uint32_t | TPR |
| Offset: 0xE40 (R/W) ITM Trace Privilege Register. | |
| uint32_t | RESERVED2 [15] |
| Reserved. | |
| __IO uint32_t | TCR |
| Offset: 0xE80 (R/W) ITM Trace Control Register. | |