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CMSIS-CORE
Version 3.00
CMSIS-CORE support for Cortex-M processor-based devices
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Structure type to access the Trace Port Interface Register (TPI).
Data Fields | |
| __IO uint32_t | SSPSR |
| Offset: 0x000 (R/ ) Supported Parallel Port Size Register. | |
| __IO uint32_t | CSPSR |
| Offset: 0x004 (R/W) Current Parallel Port Size Register. | |
| uint32_t | RESERVED0 [2] |
| Reserved. | |
| __IO uint32_t | ACPR |
| Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register. | |
| uint32_t | RESERVED1 [55] |
| Reserved. | |
| __IO uint32_t | SPPR |
| Offset: 0x0F0 (R/W) Selected Pin Protocol Register. | |
| uint32_t | RESERVED2 [131] |
| Reserved. | |
| __I uint32_t | FFSR |
| Offset: 0x300 (R/ ) Formatter and Flush Status Register. | |
| __IO uint32_t | FFCR |
| Offset: 0x304 (R/W) Formatter and Flush Control Register. | |
| __I uint32_t | FSCR |
| Offset: 0x308 (R/ ) Formatter Synchronization Counter Register. | |
| uint32_t | RESERVED3 [759] |
| Reserved. | |
| __I uint32_t | TRIGGER |
| Offset: 0xEE8 (R/ ) TRIGGER. | |
| __I uint32_t | FIFO0 |
| Offset: 0xEEC (R/ ) Integration ETM Data. | |
| __I uint32_t | ITATBCTR2 |
| Offset: 0xEF0 (R/ ) ITATBCTR2. | |
| uint32_t | RESERVED4 [1] |
| Reserved. | |
| __I uint32_t | ITATBCTR0 |
| Offset: 0xEF8 (R/ ) ITATBCTR0. | |
| __I uint32_t | FIFO1 |
| Offset: 0xEFC (R/ ) Integration ITM Data. | |
| __IO uint32_t | ITCTRL |
| Offset: 0xF00 (R/W) Integration Mode Control. | |
| uint32_t | RESERVED5 [39] |
| Reserved. | |
| __IO uint32_t | CLAIMSET |
| Offset: 0xFA0 (R/W) Claim tag set. | |
| __IO uint32_t | CLAIMCLR |
| Offset: 0xFA4 (R/W) Claim tag clear. | |
| uint32_t | RESERVED7 [8] |
| Reserved. | |
| __I uint32_t | DEVID |
| Offset: 0xFC8 (R/ ) TPIU_DEVID. | |
| __I uint32_t | DEVTYPE |
| Offset: 0xFCC (R/ ) TPIU_DEVTYPE. | |