A 64 Bit Static RAM
The row selection circuit decodes the row address and activates one single row. This row is shared by all word line signals of the row. The row selection circuit is based on a multiplexor circuit. One line is asserted while all the other lines are at zero.
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| Figure 10-33: The row selection circuit |
In the row selection circuit for the 16x4 array, we simply need to decode a two-bit address. Using AND gates is one simple solution. In figure 10-34, we present the schematic diagram of 2-to-4 and 3-to-8 decoders. In the case of very large number of address lines, the decoder is split into sub-decoders, which handle a reduced number of address lines.
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| Figure 10-34: The row selection circuit in 2 bit and 3 bit configuration |
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| Figure 10-35: The 6-bit row selection circuit using groups of 3 bits |
The 6-bit decoder of figure 10-35 is built from two stages of 3-bit decoders. A total of 64 word lines are generated using this circuit. All word lines have not been shown for clarity. The row selection circuit loads a very significant capacitance, which is the sum of Word Bit of each elementary memory cell. Consequently, the AND gate is designed using a NAND gate followed by a strong buffer (Figure 10-36).
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| Figure 10-36: Buffering the word line command |
The Row Selection circuit height should be adjusted to that of the RAM cell height. When making the final assembly between blocks, the command Edit > Move Step by Step is very useful. This command helps to move a selected block with a lambda step (Figure 10-37).
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| Figure 10-37: Moving a portion of layout step by step |
The row selection layout has the particularity to be very regular. It encrypts a binary pattern through the addition of contacts, as illustrated in figure 10-38. The binary encoding can be realized in a semi-automatic way in Microwind. The idea is to create a pattern consisting of a vertical metal box (Address lines), crossing an horizontal metal2 box, and a via to create to build an electrical link between these two nodes. The basic pattern is duplicated 6 times in X and 3 times in Y for each word line circuit. The via layer is copied only if a physical layer is needed at the intersection between vertical address lines and horizontal interconnects. The copying of the via is controlled by a Boolean table sown in figure 10-39.
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| Figure 10-38: The address uses contacts on selected address lines to program the word line according to each address |
The data matrix is filled by zeros and ones. A zero indicates that no via will be generated, a one indicates that the via will be copied. The tick Assign data must be asserted, and the via box must be chosen in this case. In the Boolean matrix, the "0" ma be changed into a "1" by a double click at the desired location.
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| Figure 10-39: Generating the matrix of contacts using the Duplicate XY command |
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| Figure 10-40: The decoder circuit and its link to the memory array |
The aspect of the row decoder circuit is shown in figure 10-40. At the left side, we recognize the regular interconnect matrix and its associated via. In the middle, the 3-input NAND gate and a buffer are designed, with the appropriate whirring and supply connections to fit exactly with the rigid layout of the static RAM cell.
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| Figure 10-41: The column selection circuit principles |
The column decoder selects a particular column in the memory array for reading the contents of the selected memory cell (Figure 10-41) or to modify its contents. The column selector is based on the same principles as those of the row decoder. The major modification is that the data flows both ways, that is either from the memory cell to the DataOut signal (Read cycle), or from the DataIn signal to the cell (Write cycle).
Figure 10-42 proposes an architecture based on n-channel MOS pass transistors. We consider here 4 columns of memory cells, which requires 2 address signals Address_Col[0] and Address_Col[1]. The n-channel MOS device is used as a switch controlled by the column selection. When the nMOS is on and Write is asserted, (Figure 10-42) the DataIn is amplified by the buffer, flows from the bottom to the top and reaches the memory through BL and ~BL. If Write is off, the 3-state inverter is in high impedance, which allows one to read the information on DataOut.
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| Figure 10-42: Row selection and Read/Write circuit |
In many cases, the DataIn and DataOut signals have a wide format, usually 8 or 16 bits. In the schematic diagram of figure 10-43, the DataIn and DataOut bus is 2-bit wide. Only one address line Address_Col[0] is required to select the appropriate columns. From a layout point of view, the nMOS transistors should fit the narrow width of the memory cell. This is usually done by stacking BL and ~BL pass MOS devices on the top of each other. Furthermore, the pass transistors should be designed with a large width to avoid any bad surprise at the write cycle.
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| Figure 10-43: Row selection and Read/Write circuit with a 2-bit DataIn and DataOut information |
The 64 bit SRAM memory interface is shown in figure 10-44. The 64 bits of memory are organized in words of 4 bits, meaning that DataIn and DataOut have a 4 bit width. Each data D0..D15 occupies 4 contiguous memory cells in the array. Four address lines are necessary to decode the one address among 16. The memory structure shown in figure 10-44 requires two address lines A0 and A1 for the word lines WL[0]..WL[3] and two address lines A2 and A3 for the bit line selection. The final layout of the 64 bit static RAM is proposed in Figure 10-45.
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| Figure 10-44: The architecture of the 64 bit RAM |
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| Figure 10-45: The complete RAM layout |
Safe read and write operations require a modification of the memory array and timing sequence, based on a precharge circuit. The usual voltage of precharge is VDD/2. Before reading or writing to the memory, the bit lines are tied to VDD/2 using appropriate pass gates. When reading, the BL and ~BL diverge from VDD/2 (Figure 10-48) and reach the "1" and "0" levels after a short time. As the static RAM cells are based on active devices (Two ring inverters), the SRAM memories usually provide the fastest read and write access times.
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| Figure 10-48: Read cycle using a precharge circuit |
A simple precharge circuit consists of a n-channel MOS or p-channel MOS (Both switch the voltage VDD/2 without degradation). The drain is connected to VDD/2, the source to the bit line (Figure 10-49).
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| Figure 10-49: Connecting a precharge circuit to all bit lines |
To further speed up the read process, analog amplifiers are used. The tiny difference is rapidly converted into a logic level, without waiting until BL and ~BL reach their final voltage (Figure 10-50).
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| Figure 10-50: Shorter read acess time thanks to a precharge circuit |
The two commonly used operational amplifier designs are shown in figure 10-51. The first amplifier is a current mirror amplifier (See chapter 11 for more details on this circuit). When Enable is on, the DataOut signal saturates either to a low or high level, depending on the voltage difference VBL-V~BL. An alternative design for the operational amplifier is also proposed. The positive feedback in the amplifier, that is the cross-coupled link between DataOut and the pMOS device permits faster sense operation than the basic circuit.
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| Figure 10-51: Very short read access time thanks to an operational amplifier |
The complete logic circuit including the Write/Read control, precharge and sense amplifier is shown in figure 10-52. When the precharge is active, all bit lines are charged to VDD/2, while all word lines are low. When the precharge is turned off, one of the world lines (WL) is active. A write operation (Write/Read=1) forces BL and ~BL to the desired value given by DataIn. A read operation (Write/Read=0) turns the write buffers off, turns the sense amplifier on, which compares the value of BL and ~BL and gives the logic result.
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| Figure 10-52: The sense amplifier used for read operation |
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| Figure 10-53: Layout of a portion of RAM with the control logic and the sense amplifier |
An implementation of the feedback sense amplifier is proposed in figure 10-54. The layout includes a portion of the 64 bit RAM, and the control logic. Parasitic loads corresponding to a 1Mb implementation are added to the vertical bit lines using virtual capacitor of 0.3pF.
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| Figure 10-54: Simulation of the sense amplifier |
The simulation shown in figure 10-54 includes two Write and two Read cycles. The first write cycle (0-3ns) writes a 1 in the desired memory cell (Mem00). The reading operation (3-5ns) confirms that the memory value is "1" (ReadData[0]). The second write cycle (5-8ns) writes a 0 in the desired memory cell (Mem00). The reading operation (8-10ns) confirms that the memory value is "0" (ReadData[0]). Notice that the write operation (Write/Read=1) forces BL and ~BL to the desired value given by DataIn. The precharge effect is clearly seen during the read operation.
