Static RAM Memory
The static RAM is a very important class of memory. It consists of two cross-coupled inverters, which form a positive feedback with two possible states illustrated in figure 10-5. This cell is also the base of many sequential circuits, as detailed in chapter 8.
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| Figure 10-5: Elementary memory cell based on an inverter loop |
The basic cell for static memory design is based on 6 transistors, with two pass gates instead of one. The corresponding schematic diagram is given in Figure 10-16. The circuit consists again of the 2 cross-coupled inverters, but uses two pass transistors instead of one. The cell has been designed to be duplicated in X and Y in order to create a large array of cells. Usual sizes for Megabit SRAM memories are 256 column x 256 rows or higher. A modest arrangement of 4x4 RAM cells is proposed in figure 10-16. The selection lines WL concerns all the cells of one row. The bit lines BL and ~BL concern all the cells of one column.
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| Figure 10-16: The layout of the 6 transistor static memory cell |
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| Figure 10-17: An array of 6T memory cells, with 4 rows and 4 columns |
The RAM layout is given in Figure 10-18. The BL and ~BL signals are made with metal2 and cross the cell from top to bottom. The supply lines are horizontal, made with metal3. This allows easy matrix-style duplication of the RAM cell.
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| Figure 10-18: The layout of the static RAM cell |
The cross-section shows the nMOS devices and the connection to VSS using metal3, situated on the middle of the cell. The BL and ~BL lines, in metal2 are on both sides. The word line controls the access between the bit lines and the internal memory information.
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| Figure 10-19: Cross-section of the static RAM cell in the n-channel MOS region |
The size of the static RAM is given in the menu Layout size, accessible through the command File > Properties. As shown in figure 10-20, the layout dimensions are 41x46 lambda.
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| Figure 10-20: Size of the static RAM cell can be found in the Properties menu |
WRITE CYCLE. Values 1 or 0 must be placed on Bit Line, and the data inverted value on ~Bit Line. Then the selection Word Line goes to 1. The two-inverter latch takes the Bit Line value. When the selection Word Line returns to 0, the RAM is in a memory state.
READ CYCLE. The selection signal Word Line must be asserted, but no information should be imposed on the bit lines. In that case, the stored data value propagates to Bit Line, and its inverted value ~Data propagates to ~Bit Line.
SIMULATION. The simulation parameters correspond to the read and write cycle in the RAM. The simulation steps proposed in figure 10-21 consist in writing a 0, a 1, and then reading the 1. In a second phase, we write a 1, a 0, and read the 0. The Bit Line and ~Bit Line signals are controlled by pulses. The floating state is obtained by inserting the letter "x" instead of 1 or 0 in the description of the signal.
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| Figure 10-21: Proposed stimulation patterns for the simulation of the 6T static Ram memory |
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| Figure 10-22: The bit Line pulse used the "x" floating state to enable reading the memory cell |
The simulation of the RAM cell is proposed in figure 10-23. At time 0.0, Data reaches an unpredictable value of 1, after an unstable period. Meanwhile, ~Data reaches 0. At time 0.5ns, the memory cell is selected by a 1 on Word Line. As the Bit Line information is 0, the memory cell information Data goes down to 0. At time 1.5ns, the memory cell is selected again. As the Bit Line information is now 1, the memory cell information Data goes to 1. During the read cycle, where Bit Line and ~Bit Line signals are floating, the memory sets these wires respectively to 1 and 0, corresponding to the stored values.
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| Figure 10-23: Write cycle for the static RAM cell |
