Dynamic RAM

The dynamic RAM memory has only one transistor, in order to improve by almost one order of magnitude the memory matrix density. The storage element is no more the stable inverter loop as for the static RAM, but only a capacitor Cs, also called the storage capacitor. The DRAM cell architecture is shown in figure 10-56.

Figure 10-56: The 1 transistor dynamic RAM cell

Figure 10-57: Simulation of the Write cycle for the 1 transistor dynamic RAM cell

The write and hold operation for a "1" is shown in figure 10-57. The data is set on the bit line, the word line is then activated and Cs is charged. As the pass transistor is n-type, the analog value reaches VDD-Vt. When WL is inactive, the storage capacitor Cs holds the "1".

Figure 10-58: Simulation of the Read cycle for the 1 transistor dynamic RAM cell

The reading cycle is destructive for the stored information. Suppose (Figure 10-58) that Cs holds a 1. The bit line is precharged to a voltage Vp (Usually around VDD/2). When the word line is active, a communication is established between the bit line, loaded by capacitor CBL, and the memory, loaded by capacitor CS. The charges are shared between these nodes, and the result is a small increase of the voltage Vp by ΔV, thanks to the injection of some charges from the memory. Now, if the Cs was holding a zero, the activation of the word line result in a small decrease of the precharge voltage, to Vp -ΔV.

In summary, the bit line voltage Vp+ΔV means that the memory state was 1, the voltage Vp-ΔV means that the memory state was 0. We say "was" because the memory information is destroyed by the reading cycle. What the DRAM memory must do is to convert the +/-ΔV into 1/0, and rewrite the memory for a future read cycle.

DRAM Memory Cell

The DRAM memory cell should be as small as possible, but with the highest possible value for the storage capacitor Cs. The first idea, shown in figure 10-59, consists in using the parasitic junction capacitance as the storage capacitor Cs. The polysilicon gate is shared by all word lines in the same row, and the metal interconnect is shared by all bit lines in the same column. The capacitor Cs is around 0.1fF in 0.12µm technology. Notice that the bit line contact may be shared by two memory cells to improve the density.

Figure 10-59: A DRAM memory design using parasitic junction capacitance

There are two main problems with this design: first, the capacitance is very small, because the junction capacitance do not have a very high value, second, a leakage exists between the capacitor Cs and the bit line, through the access transistor, even when a zero voltage is applied on the bit line. Consequently, the charges stored in the capacitor tend to disappear, which means that the memory information is retained only for less than one µsecond (Figure 10-60).

Figure 10-60: Leakage current in the dynamic RAM based on a junction capacitance

The leakage current may be reduced by using low leakage MOS devices, non-minimal channel length, but the best technique is to increase by 2 or 3 orders of magnitude the storage capacitor. Commercial Dynamic RAM memories use storage capacitors with a value between 10fF and 50fF. This is done by creating a stacked capacitor for the storage node (Figure 10-61), thanks to the following technological advances: use of specific buried layer to create a high quality capacitor, enlarged plate area thanks to a thicker distance between the substrate surface and metal1, and a 3D construction of the capacitor, and use of high permittivity dielectric oxide. The silicon dioxide SiO2 has a relative permittivity ε_r of 3.9. Other oxides are also compatible with the CMOS process: the Si₃N₄ (ε_r =7), and Ta₂O₅ (ε_r =23).


Figure 10-61: Increasing the storage capacitance (Left: junction capacitor, right, embedded capacitor)

The drawback of these methods is the addition of specific process steps to build the 3D capacitor, including delicate fabrication of high dielectric materials. The additional processing steps for the embedded DRAM represent approximately a 25% cost over the basic process. In Microwind, the high capacitance memory can be generated using the option layer, as shown in figure 10-62. The option layer is placed at the intersection of the n-diffusion area and the VSS metal line.

Figure 10-62: The option layer configured for the embedded capacitor

Figure 10-63: Cross-section of the DRAM cell with an embedded capacitor

The cross-section of the DRAM capacitor is given in figure 10-63. The bit line is routed in metal2, and is connected to the cell through a metal1 and diffusion contact. The word line is the polysilicon gate. On the right side, the storage capacitor is a sandwich of conductor material connected to the diffusion, a thin oxide (SiO2 in this case) and a second conductor that fills the capacitor and is connected to ground by a contact to the first level of metal. The capacitance is around 20fF is this design. Higher capacitance values may be obtained using larger option layer areas, at the price of a lower cell density. A DRAM array is shown in figure 10-64, together with a vertical cross-section at the capacitor location.


Figure 10-64: The stacked capacitor cell compared to the diffusion capacitor cell