CMOS Design > Memories

ROM Memory

The most simple non-volatile memory consists of a layout in which the data is permanently written through a specific layout arrangement and cannot be change by the user once fabricated. The two logic states are shown in figure 10-67. The basic patterns for a "1"' can consist of the existence of a n-channel MOS, the "0" by an open circuit. The logic programming is part of the fabrication process. ROM memories are used for storing microprocessor programs, mathematical values such as a sampled sinusoidal data for waveform generators, etc.. The size of ROM memories is usually small as compared to other embedded memories, because the contents cannot be changed.

Figure 10-67: Changing the status of the memory point by a diffusion layer

We may create an array of ROM memory that stores the string "Hello!", which corresponds to the following binary data stream (Table 10-2).

The ROM architecture proposed in figure 10-68 is a NOR-like circuit [Haraszti]. The upper PMOS transistor precharges the vertical bit lines to VDD. Depending on the address, a high voltage is applied on one word line (WL[1] in the example), while all other word lines are kept a low potential. The selected word line turns all programmed transistors on, which result in a discharge towards VSS, while bit lines with unprogrammed transistors remain on high voltage. The inverters situated on the lower part of the ROM array refresh and invert the bit line information, which is sent to the display. Notice that the precharge effect is not simulated at logic level. When the precharge is off, all bit line nodes are considered in 3-state, without any consideration of a "low 3-state" level or "high 3-state" level, which is supported in professional logic simulators.

Figure 10-68: Delivering the contents of the ROM memory

In DSCH, the hexadecimal display has been configured to display the character corresponding to the ASCII input information (Figure 10-69).

Figure 10-69: The hexadecimal display configured in ASCII mode

Layout considerations

The basic cells shown in figure 10-70. The transistor situated on the left ("1") creates a low resistance path between the bit line and the ground when the word line is high. The layout corresponding to "0" is not a transistor, as the diffusion has been removed. The polysilicon ensures the continuity of the word line information, while the metal 2 ensures the continuity of the bit line information. The cell used for duplication in X and Y is also shown.

Figure 10-70: The basic patterns of the ROM memory

Figure 10-71: Programming the ROM memory during the duplication phase

The duplication in X and Y can be programmed according to a binary information, through the menu shown in figure 10-71 (Edit > Duplicate X,Y in Microwind). The first step consists in giving the desired X and Y size, 8 in this example. Secondly, we choose the layout box that will be affected by the logic information. In our case, we select the n-diffusion box used for the channel. The selected layout box in marked by the cross in the layout window. Finally, we enter the desired information in hexadecimal format, and we click Fill Array to transform the string of data into elementary binary information. After a click on Generate, the regular ROM layout appears as shown in figure 10-72, which contains the binary version of the string " Hello! ".

Figure 10-72: The ROM memory stores the string "Hello!" in binary format

Figure 10-73: The ROM memory cross-section

The cross-section (Figure 10-73) reveals the diffusion programming which creates or not the path to ground. If no channel is fabricated, the memory cell is equal to a zero. When the channel exists, the memory cell is equal to a one.

CMOS Design > Memories > ROM Memory