| CMOS Design > Analog Cell Design | |
Could the logic CMOS inverter act as an amplifier? In principles, yes, as the static characteristics of the CMOS amplifier is very much like the static response of the basic amplifier described earlier. The main problem is the very high gain of the amplifier. When trying to compute the slope, we find 180. To operate in the amplifier zone, we should inject a signal around 1.20V, otherwise there is no chance to take advantage of the very high amplification.
Furthermore, as the process parameters are not well controlled, the commutation point of the inverter may fluctuate in a significant range, depending on the location of the die on the wafer, or even on the die itself. As a consequence, very high gain structures are not adequate. Usually, amplifiers with gain around 10 (that is 20dB) are used, for example in the low noise input amplifier of the GSM.
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The single-stage amplifier described here consists of a MOS device (we choose here a n-channel MOS) and a load resistance. The resistance can be made from polysilicon or diffusion. As the gain of this amplifier is proportional to the load resistance, a MOS device with gate and drain connected could replace the resistance. This is called an active resistance. Using a small silicon area, high resistance can be obtained, meaning high amplifier gains.
The range of voltage input that exhibits a constant gain appears clearly. For VDS higher than 0.6V and lower than 0.8V, the output gain is around 5. Therefore, an optimum offset value is 0.11V.
We define the transconductance gm as the derivative of iDS versus vDS. Thus gm is the invert of the channel resistance. Using the very simple approximation of the MOS current in saturation, a formulation of gm in saturation is obtained. Thus, the gain of the amplifier can be expressed by (5).
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To further increase the gain, the ratio between the active load resistance and the n-channel MOS resistance should be increased.
The goal of the differential amplifier is to compare two analog signals, and to amplify their difference.
The differential pair is built from n-channel MOS devices. Their size must be identical, and drawn with the same orientation, to minimize the offset generated by transistor mismatch.
The differential amplifier formulation is reported below. Usually, the gain K is high, ranging from 10 to 1000. The consequence is that the differential amplifier output saturates very rapidly, because of the supply voltage limits.
Vout=K(Vp-Vm)
In the simulation, it can be seen that a small voltage difference between V+ and V- induces the saturation of the output either near VSS and VDD.
The push-pull amplifier is built using a voltage comparator and a power output stage. Its schematic diagram is reported in the figure. The difference between V+ and V- is amplified and it produces a result, codified : Vout.
The gain near 2.5V is more than 1,000. Use the Voltage vs. Voltage simulator mode to get the transfer characteristics Vout/V+. The input range is around 0.5V to 4.0V.
You can easily build a follower by designing an extra connection from Vout to V-. The output stage is not strong enough to be able to drive large loads such as output pads.
| CMOS Design > Analog Cell Design > Amplifier | |