Phase-Lock Loop

Phase Detector
Filter
Voltage Controlled Oscillator for PLL
Complete Phase Lock Loop

The phase-lock-loop (PLL) is commonly used in microprocessors to generate a clock at high frequency (F_out=2GHz for example) from an external clock at low frequency (F_ref= 100MHz for example). The PLL is also used as a clock recovery circuit to generate a clock signal from a series of bits transmitted in serial without synchronization clock (Figure 12-50). The PLL may also be found in frequency demodulation circuits, to transform a frequency varying waveform into a voltage.

Figure 12-50. Principles of phase lock loops

The PLL uses a high frequency oscillator with varying speed, a counter, a phase detector and a filter (figure 12-51). The PLL includes a feedback loop which aligns the output clock ClkOut to the input clock ClkIn through a phase locking stabilization process. When locked, the high input frequency f_out is exactly N. ƒ_in. A variation of the input frequency ƒ_in is transformed by the phase detector into a pulse signal, which is converted into variation of the analog signal Vc. This signal changes the VCO frequency, which is divided by the counter and changes clkDiv according to ƒ_in.

Phase Detector

The most simple phase detector is the XOR gate. The XOR gate output produces a regular square oscillation PD_Out when the input clkIn and the signal divIn have one quarter of period shift (or 90° or π/2). For other angles, the output is no more regular. In figure 12-52, two clocks with slightly different periods are used in Dsch2 to illustrate the phase detection.

Figure 12-52. The XOR phase detector at work

At initialization, (Figure 12-52) the average value of the XOR output V_PD is close from 0. When the phase between clkDiv and clkIn is around Π/2, V_PD is VDD/2. Then it increases up to VDD. Consequently, V_PD and the phase difference are linked by expression 12-10. For example, when ΔΦ=Π/2, V_PD is VDD/2.

(Equ. 12-10)

The gain of the phase detector is the ratio between V_PD and ΔΦ. The gain is often written as K_PD, with an expression derived from equation 12-10, which is valid for ΔΦ between 0 and π, as drawn in figure 12-53.

(Equ. 12-11)

Figure 12-53. The XOR phase detector at work

When the phase difference is larger than π, the slope sign is negative until 2π. When locked, the phase difference should be close to π/2.

Filter

The filter is used to transform the instantaneous phase difference V_PD into an analog voltage V_c which is equivalent to the average voltage V_PD. The rapid variations of the phase detector output are converted into a slow varying signal V_c which will later control the voltage controlled oscillator. Without filtering, the VCO control would have too rapid changes which would lead to instability. The filter may simply be a large capacitor C, charged and discharged through the R_on resistance of the switch. The R_on.C delay creates a low-pass filter. Figure 12-54 shows an XOR gate with the output charged with a large poly/poly2 capacitor and a serial resistance to create the desired analog voltage control V_c.

Figure 12-54. Large load capacitance and weak XOR output stage to act as a filter

Figure 12-55. Response of the phase detector to slightly different input clocks

In the figure above, the filtered version of the XOR gate output VPD is shown. It can be seen that VPD is around VDD/2 when the phase difference is Π/2 or -Π/2. The duty cycle of the phase detector output should be as close as possible to 50%, so that Vc is very close to VDD/2 when the inputs are in phase. If this is not the case, the PLL would have problems locking or would not produce a stable output clock. The XOR gate layout has been modified so that the output voltage Vc is very close to VDD/2 when one input in fixed to ground and the other input is a regular clock.

Voltage Controlled Oscillator for PLL

Important characteristics of the PLL can be listed:

The oscillating frequency should be restricted to the required bandwidth. For example, in European mobile phone applications, the VCO frequency should be varying between f_low=1700 and f_high=1800MHz (Figure 12-56).
Due to process variations, the VCO frequency range should be extended to f_min, f_max, typically 10% higher and lower than the request range (figure 12-56).
When the control voltage Vc is equal to VDD/2, the VCO clock should be centered in the middle of the desired frequency range.
The duty cycle of the VCO clock output should be as close as possible to 50% [Baker]. If this is not the case, the PLL would have problems locking or would not produce a stable output clock.

Figure 12-56. Requirements for the VCO used in the PLL

The current starved oscillator can be used as a VCO for the phase lock loop, with a modification of its voltage control circuit so that the center frequency is 2450MHz at Vc=VDD/2, and the frequency range do not exceed 2800MHz and do not drop lower than 1800MHz. The modification consists in providing a permanent current path through Rvdd2 to VDD/2 (Figure 12-57), which helps keeping Vc around VDD/2. When VPD is VDD, Vc is increased and the VCO frequency is close to f_max. When VPD is 0, Vc is lowered and the VCO frequency is close to f_min.

Figure 12-57. Connecting the current-starved VCO to the phase detector

A second important sub-circuit added in the PLL is the precharge to VDD/2. The nMOS device controlled by Vc_Prech helps the big capacitor Cfilter to reach VDD/2 during the first nanoseconds. This precharge circuit speeds up the locking of the PLL.

Complete Phase Lock Loop

The implementation of the PLL shown in figure 12-58 is a direct copy of the schematic diagram of figure 12-57. Notice that the resistor Rfilter (1000Ohm) and Rvdd2 (5000 Ohm) have been implemented using virtual elements and not physical resistance. The same can be said for the capacitor Cfilter (0.3pF). However, these resistance and capacitance are easy to integrate on-chip.

Figure 12-58. Connecting the current-starved VCO to the phase detector

The input frequency is fixed to 2.44GHz. During the initialization phase (Simulation of figure 12-59), the precharge is active, which pushed rapidly the voltage of Vc around VDD/2. The VCO oscillation is started and the phase detector starts operating erratically. The output Xnor is an interesting indication of what happens inside the phase detector. We see that the phase difference is very important during the first 10 nanoseconds. Then, the VCO output starts to converge to the reference clock. In terms of voltage control, Vc tends to oscillate and then converge to a stable state where the PLL is locked and stable. The output is equal to the input, and the phase difference is equal to one fourth of the period (Π/2) according to the phase detector principles.

Figure 12-59. Simulation of the PLL showing the locking time